1. Field of the Invention
The present invention relates to an information processing system, calculation nodes, a control method of the information processing system, and more specifically, to an effective technology applied to information processing technology etc. such as parallel processing by load sharing using a plurality of calculation nodes.
2. Description of the Related Art
High-performance computers, which can imitate various physical phenomena in nature or in manufactured products as realistically as possible, are used for design and simulation in fields of nuclear energy, automotive engineering, marine vessel engineering, aeronautics, high-rise building design and so forth. In recent years, they are also utilized in biological and chemical fields such as molecular design and gene analysis, and the sites where they are utilized are not only universities and research institutions but also business enterprises.
For a method of realizing the above high-performance computers, in order to speed up a massive number of repeated operations such as matrix calculations, often used in scientific and technological fields, a method of performing parallel processing using a special kind of computer, called a vector processor, had been the mainstream. However, drastic performance gains and reduction in price of microprocessors of general purpose computers has recently caused an increased use of a parallel processing method, which has a large number of microprocessors operating in parallel.
In such a parallel processing method, which has a large number of microprocessors operating in parallel, the performance of the network inter-connecting the microprocessors and improvements in the communication efficiency thereof influence the performance of the high-performance computers.
A technology disclosed in Patent Document 1, for example, has been heretofore known as a technology relating to such a parallel processing method.
In a technology in Patent Document 1, in all-to-all communication where all of a plurality of processors constituting a parallel computer, transmit different messages to other processors, phase control means according to the number of processors constituting a parallel computer is provided to each processor. Predetermined information relating to a transmission source processor and a transmission destination processor determined in advance are stored in the phase control means, in execution of all-to-all communication, each processor determine its own transmission timing for each phase by referring to the phase control means. By so doing, conflict of the communication on a Torus network inter-connecting the processors can be avoided, realizing efficient all-to-all communication.
The technology in Patent Document 1 is useful from the point of avoiding conflict between processors on a communication path, however increase in communication capacity in the communication path connecting the processors is not considered.
Therefore, in order to improve performance of a parallel computer, it is required to increase the communication capacity between processors (nodes). Flexible and high-speed change of communication capacity between nodes is also required due to frequent changes in communication capacity between connected nodes.
Meanwhile, for further improvement of a parallel computer, it is required to have a higher degree of parallelism of a number of processors. In such a case, an attempt to connect a large number of nodes by multiplexing communication cables alone would require laying a large number of cables, causing problems such as an increase in implementation space and complications of control. Therefore, it is crucial to reduce the number and the length of the communication cables. Patent Document 1: Japanese unexamined patent publication bulletin No. 05-151181